
List Of Figures
System Reference, January 2001
11
List Of Figures
Figure 1 P- and C-Models of the Agilent93000 SOC Series 18
Figure 2 The Agilent 93000 SOC Series Tester 19
Figure 3 Test Processor-per-pin Architecture 20
Figure 4 SOC System Integration 21
Figure 5 SOC Series Model with 960/1024 Pins Testhead 23
Figure 6 SOC Series Model with 448 Pins Testhead 24
Figure 7 Agilent 93000 SOC Series Testhead 25
Figure 8 Manipulator 26
Figure 9 Support Rack 27
Figure 10 Cooling Unit 28
Figure 11 HP Workstation 29
Figure 12 ON/OFF Switches on Support Rack Front Panel 32
Figure 13 ON Button 33
Figure 14 Standby Button 35
Figure 15 Line Switch in OFF position 35
Figure 16 Tester Electronics Inside a 512 Pins Testhead 39
Figure 17 DPS Connection 40
Figure 18 Channel Boards 41
Figure 19 Channel Board Electronics 42
Figure 20 Clock Board 43
Figure 21 Pin PMU and Board ADC 45
Figure 22 Multiplexed AD Conversion of Parallel Pin PMU Measurements 46
Figure 23 Connecting the High-Precision PMU to a Channel Board 47
Figure 24 Coherent Sampling 49
Figure 25 Master Clock Distribution on 512-Pin Testhead 53
Figure 26 Master Clock Distribution on 1024-Pin Testhead 54
Figure 27 Card Cage Positions within Test Head (Topview from DUT Board
Side) above their Corresponding SOC Series Testers.
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Figure 28 Input of a card cage 60
Figure 29 Position of DUT board above the Test Head. 61
Figure 30 DUT board options depending on test head size 63
Figure 31 1. Allocation of the 512 pin DUT board’s groups to the card cages of
the 512 pin test head. 2. Numbering of pairs of pad blocks.
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Figure 32 1. Allocation of the 1024 pin DUT board’s groups to the card cages
of the 1024 pin test head. 2. Numbering of pairs of pad blocks.
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Figure 33 A Pair of Pad Blocks (No. 228) 67
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